A Novel Technique to Minimize Stand by Leakage Power in Nanoscale Cmos Vlsi

Pardeep Jamwal, V.V.S.S. Ravi Kiran, S. Krishna Kishore, P. Ravi Kumar And K. Satish Reddy

Chaitanya Engineering College (India).

DOI : http://dx.doi.org/10.13005/msri/060213

ABSTRACT:

This paper proposes a novel approach to minimize leakage currents in CMOS circuits during the off-state (or standby mode, sleep mode) by applying the optimal reverse body bias to the substrate (body or bulk) to increase the threshold voltage of transistors. The optimal bias point is determined by comparing the sub-threshold current (ISUB) and band-to-band current (IBTBT) simultaneously. The proposed circuit was simulated in HSPICE using 90nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperature (ranging from 25oC to 100oC). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25oC and 100oC on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces considerable amount of the leakage power in the nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop. Keywords- off-state, standby mode, sleep mode, leakage currents, sub-threshold leakage current, band-to-band tunneling (BTBT) leakage current.

KEYWORDS: Leakage power; Nanoscale CMOS technology

Copy the following to cite this article: Jamwal P, Kiran V. V. S. S. R, Kishore S. K, Kumar P. R, Reddy K. S. A Novel Technique to Minimize Stand by Leakage Power in Nanoscale Cmos Vlsi. Mat.Sci.Res.India;6(2)

Copy the following to cite this URL: Jamwal P, Kiran V. V. S. S. R, Kishore S. K, Kumar P. R, Reddy K. S. A Novel Technique to Minimize Stand by Leakage Power in Nanoscale Cmos Vlsi. Mat.Sci.Res.India;6(2). Available from: http://www.materialsciencejournal.org/?p=3538

---

This work is licensed under a Creative Commons Attribution 4.0 International License.